semiconductores :: calidad y medio ambiente:: aseguramiento de la calidad


Quality Management

Quality Assurance
>Certificates
>Quality policy
>TQM milestones
>Quality by design
>Supplier evaluation
>Quality assurance
>Reliability tests
>Basis of reliability tests
>Partnerships

Environmental Policy
>Ozone Depleting Substances
>RoHS Directive
>Lead-Free Status
>RoHS & ELV Compliance
>Product Identification
>Material Composition Declaration (MCD)

 

 

 

 

  
 
Reliability Tests

Fagor Electronica, S. Coop. assures the continued Reliability of its products through a system of process qualification and random sampling of Production lots. Testing of products in conjunction with rigorous statistical analysis is the best way to control the product Reliability.

 
Diodes reliability tests
 
Test
Conditions
Acceptance Criteria
Efficient for processes of
Failure due to
High Temperature Reverse Bias (HTRB)
Tj= 150ºC, V=80%Vrrm, 1000h AEC-Q101 rev.C
0/77
Passivation Chip Singulation Moulding
Surface charges accumulation.
High Temperature Storage (HTS)
Ta=150ºC, 1000h MIL STD 750C.1032
0/77
Diffusion Passivation Metallization Die Attach Moulding Quality of row materials. Cleanliness of processes.
Contact degradation. Corrosion.
Intermittent Operating Life (IOL)
Tj=Tj max 10,000 cycles AEC-Q101 rev.C
0/77
Metallization Die Attach
Contact degradation.
Thermal Cycling
-55ºC/+150ºC 1,000 cycles AEC-Q101 rev.C
0/77
Passivation Chip Singulation Metallization Die Attach Moulding
Thermal mismatch between chip and package
Pressure Cooker Autoclave (PCT)
T=121ºC, 100%RH, 2 atm., 96h AEC-Q101 rev.C
0/77
Metallization Die Attach Moulding
Poor hermeticity. Contamination. Corrosion.
Resistance to Solder Heat
T= 260 °C ,10 sec. Preconditioning in SMD at MSL=1 AEC-Q101 rev.C
0/30
Metallization Die Attach Moulding
Poor hermeticity. Chip damage.
Solderability
T=245ºC, 3 sec. 1h steam aging AEC-Q101 rev.C
0/10
Electroplating / Dipping
Plating conditions or plating material
Lead Strength
AEC-Q101 rev.C
0/10
Lead integrity
Chip damage. Broken leads

Preconditioning in Surface Mounted Devices SMD at Moisture Sensitivity Level MSL=1 according to JEDEC standard JSTD - 020C.
 
Thyristors reliability tests
 
Test
Conditions
Acceptance Criteria
Efficient for processes of
Failure due to
High Temperature Forward/Reverse Bias (HTFB/HTRB)
Tj= 125ºC, V=80%VDRM, 1000h MIL STD 750C.1027 JESD 22-A108
0/77
Passivation Chip Singulation Moulding
Surface charges accumulation.
High Temperature Storage (HTS)
Ta=125ºC, 1000h MIL STD 750C.1032
0/77
Diffusion Passivation Metallization Die Attach Moulding Quality of row materials. Cleanliness of processes.
Contact degradation. Corrosion.
Intermittent Operating Life (IOL)
Tc=55ºC Tj=Tj max 10,000 cycles MIL STD 750C.1037
0/77
Metallization Die Attach
Contact degradation.
Thermal Cycling
-55ºC+150ºC 1,000 cycles MIL STD 750C.1051-2 JESD 22 -A-104
0/77
Passivation Chip Separation Metallization Die Attach Moulding
Thermal mismatch between chip and package
Pressure Cooker Autoclave (PCT)
T=121ºC, 100%RH, 2 atm., 96h JESD 22 - A-104
0/77
Metallization Die Attach Moulding
Poor hermeticity. Contamination. Corrosion.
Resistance to Solder Heat
T= 260 °C ,10 sec. Preconditioning in SMD at MSL=1. JESD22-B-106-A
0/30
Metallization Die Attach Moulding
 Poor hermeticity. Chip damage.
Solderability
T=245ºC, 3 sec. 1h steam aging MIL STD 750C.2026 JESD22-B102D Method 1
0/10
Electroplating / Dipping
Plating conditions or plating material
Lead Strength
MIL-STD-750 Method 2006
0/10
Lead integrity
Chip damage. Broken leads.
 
Preconditioning in Surface Mounted Devices SMD at Moisture Sensitivity Level MSL=1 according to JEDEC standard JSTD - 020C.