Fagor Electronica, S. Coop. believes that the
Reliability of a product starts with the design. Therefore,
meticulous care is put in the design and manufacturing stages.
According to our Quality System procedure, we assure that
the products developed comply with the specified requirements
and the development of them is focused on prevention to eliminate
the appearance of possible problems in subsequent phases of
the process.
This policy is implemented throughout a mandatory New Process
/ Product Qualification Procedure. Before releasing to manufacturing
a new product or a major process change, it must be verified
by QC department that the design meets mentioned procedure,
which is based on the CDF-AEC-Q101 Stress Test Qualification
for Automotive Grade Discrete Semiconductors.
Main tools used are:
Definition of customers needs by means of QFD.
Failure Mode and Effect Analysis (FMEA) to improve the Quality
of the designs.
Design of Experiments (DOE) to find out the better solutions.
Value analysis to avoid or minimize not added value processes.
Statistical Process Monitoring (SPM) and Statistical Process
Control (SPC) to monitor the performance of products and processes.
Tests applied are selected according
to the Failure Mode Effect Analysis performed at design and
according to the application conditions of the products. These
tests are oriented to the package and to the chip performance
and also to find out and to accelerate the failure mechanism.
Diodes
Characterization
Characterization
@ 25ºC
Characterization
@ 150ºC
Vf: Max.Forward voltage @ If.
Vf: Max. Forward voltage @ If.
Ir: Max. Reverse current @ Vrrm.
Ir: Max. reverse current @ Vrrm.
Vbr: Breakdown voltage @ 0.1mA
Vbr: Breakdown voltage @ 0.1mA
Trr: Max. reverse recovery time from
If = 0.5A ; Ir =1A ; Irm = 0.25A
trr: Max. reverse recovery time from If
= 0.5A ; Ir =1A ; Irm = 0.25A
Definition of customers needs by means of QFD.